1. Field of the Invention
The present invention relates to semiconductor devices and method for forming the same and, more particularly, to a method for fabricating a semiconductor device which is suitable for increasing process tolerance in the step of forming pad polysilicon layers.
2. Discussion of the Related Art
In a conventional semiconductor device, a pad polysilicon layer is formed after cell transistors are formed. The polysilicon layer has a predetermined height for contacting the source and drain regions of the cell transistors to increase process margin in the subsequent process steps. Using this structure, a DRAM (Direct Random Access Memory) having a capacitor over bitline (COB) structure can enhance alignment tolerance. Moreover, in forming a contact hole for contacting a bitline, the aspect ratio of the contact hole is not high due to the presence of the pad polysilicon layer. For this reason, researches and development have been directed to forming the COB structure.
A conventional method for fabricating a semiconductor device will be described with reference to FIGS. 1a to 1e which are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
Referring to FIG. 1a, a device isolation layer is formed on a semiconductor substrate 10 to define an active region, on which cell transistors 1 are then formed.
Referring to FIG. 1b, an oxide layer 2, which functions as an insulating layer, is deposited on the entire surface including the cell transistors 1. Subsequently, a planarization insulating layer 3 is deposited on the oxide layer 2.
Referring to FIG. 1c, the planarization insulating layer 3 and the oxide layer 2 are selectively removed by a photolithography process to form pad contact holes 4, so that source and drain regions of the cell transistors 1 are exposed. The pad contact holes 4 are formed according to the minimum design rule of corresponding devices. For example, for a 256 A Mask, pad contact holes of 0.225.times.0.225 .mu.m.sup.2 size are formed.
Referring to FIG. 1d, a polysilicon layer 5a is formed on the entire surface and in the pad contact holes 4.
Referring to FIG. 1e, the polysilicon layer 5a is selectively etched by using a pad mask to form pad polysilicon layers 5b. The pad polysilicon layers 5b are not formed according to the minimum design rule and have a fine pattern size. For example, the width of the pad polysilicon layer 5b is 0.4 and the spacing between the pad polysilicon layers 5b is 0.2. Then a planarization insulating layer (not shown) is formed to begin formation of a capacitor.
As described above, after forming the cell transistors 1, pad polysilicon layers 5b of a predetermined height are formed to contact with the source and drain regions of the cell transistors 1, thus increasing process tolerance of the semiconductor device.
This conventional method for fabricating a semiconductor device, however, has problems. Although process tolerance may be increased by forming pad polysilicon layers, since pad contact holes are formed based on the minimum design rule, tolerance for the patterns used in the step of forming pad contact holes is low. Moreover, since pad polysilicon layers have fine pattern sizes, it is difficult to form precise patterns of pad polysilicon layers on the substrate.